Power and bias validation — V3.3
The canonical design contains 356 components. The checks below found and corrected an unsupported reference load, an unverifiable quad amplifier MPN, two shutdown-current paths, and excitation-buffer sensitivity to harness capacitance. These are analytical and typical-model results; prototype measurements remain the release conditions listed below. Machine-readable inputs/results and rerunnable original-model decks are in simulation/power_validation.
| Check | Evidence | Result |
|---|---|---|
| Reference capacitive load | REF3330 datasheet, capacitor tolerances | Supported 0.1–10 µF; selected reservoir maximum 9.493 µF over −40…85°C under stated component tolerances |
| Reference load/headroom | 600 µA ADC maximum +250 µA divider | 850 µA <2 mA; 70 mV maximum dropout at ±2 mA and −40…85°C |
| VEXC buffer | Original MCP6001/2/4 POLY macro model, 25°C | Dual feedback passes selected 0.8–2 µF capacitance cases; 5 mA step settles within 0.1% in 4.434 ms |
| VMID buffer | Twenty actual passive filter branch networks, other amplifier outputs held at AC ground | With 1 nF extra direct capacitance, 0.0204 dB peaking and 2.47% overshoot; complete active-chain/overload coupling remains a separate test |
| Shutdown injection | Actual resistor and diode topology | VMID-divider input limited to 0.266 mA; excitation divider estimate 1.50 mA; TLV755 output-to-input Schottky added |
| Active current | Datasheet maxima plus explicit switching/MCU allowances | 64.405 mA engineering allocation; measured mode peaks and USB startup current still required |
| Charging | Seeed schematic and BQ25101 timer | 100 mA selection fits cell's standard charge rating and approximately 5 h ideal CC; default 50 mA can encounter the 9.44–12.5 h safety timer |
| Standby | Whole module and breakout topology | External IMU breakout LED/LDO and battery divider remain powered; whole-kit sleep current requires measurement |
Circuit corrections
Reference: REF3330AIDBZR replaces MCP1501. The original MCP1501 directly drove about 20 µF despite its 10 nF direct-load limit. The new 3.0 V reference feeds the ADC and a 2 kΩ /10 kΩ divider; the existing buffers retain VEXC=2.5 V and VMID=1.25 V. C_ADC_REF is TAJA685K010RNJ, 6.8 µF, 10 V, ±10%, case A; C_REF is 1 µF ceramic. Maximum combined capacitance is 6.8×1.1×1.10 +1×1.1×1.15 =9.493 µF. Conservative effective minimum is 5.508 µF from the tantalum alone; ceramic DC-bias contribution is omitted from that lower bound. This is a prototype variation from MCP33131's application guidance for a 10 µF, 10 V tantalum reservoir. The 600 pC conversion-charge proxy derived from 600 µA at 1 Msps gives 109 µV droop on 5.508 µF, approximately 1.19 differential LSB at 3 V. Average current does not guarantee the actual pulse-charge maximum or ESR spike; measure both before accepting ADC noise performance. Tantalum ESR is specified up to 4 Ω at 100 kHz, while the parallel ceramic supplies faster current.
REF3330 guarantees up to 70 mV dropout at ±2 mA over −40…85°C; its full line/load accuracy conditions use VIN≥3.2 V. A 3.3 V rail at −2.5%, minus a conservative 13 mV switch drop, is 3.2045 V: approximately 134.5 mV of regulation margin, only 4.5 mV against the full-accuracy condition. This calculation is a screening estimate. The XIAO SGM2040 UTDFN regulator's loaded maximum-dropout figure is specified at 25°C, and its accuracy test conditions differ from battery operation near 3.6 V. Acquisition therefore uses a 3.6 V battery floor and requires measured rail qualification over temperature. Reference startup at the selected reservoir is not covered by a guaranteed transient model.
Buffers: VEXC uses 47 Ω from raw amplifier output to the load, 10 kΩ from load to inverting input, 100 nF from raw output to inverting input, and 1 µF at the load. Remote DC feedback avoids the load-dependent 235 mV drop a plain 47 Ω resistor would introduce at 5 mA. With all twenty pressure resistors at their maximum 5 mA aggregate load, the typical model gives 2.49925 V output and approximately 2.734 V raw output. A simultaneous 0→5 mA step reaches 2.28850 V and recovers to within 0.1% in 4.434 ms, inside a 20 ms pressure-sampling period. Samples taken during that transient need appropriate timing/qualification. The original direct buffer with 10 nF has 6.74 dB peaking and 46.7% overshoot, which motivated this change.
The VMID filter capacitances total 244 nF, but connect through the two filter RC networks rather than directly to ground. The deck preserves those passive networks for all twenty channels. The 100 pF–1 nF direct-parasitic cases behave well in the typical model; 10 nF creates 6.61 dB peaking and is outside the demonstrated load envelope. This test does not establish phase margin across process/temperature or include all active filter loops and diode overload currents. Root signal-chain verification owns those checks. R_VMID_IN=4.7 kΩ limits the held 1.25 V divider capacitor's injection during rail collapse; it is not a series element in the VMID output distribution.
Shutdown: TPS22919 QOD is correctly enabled: pin 5 is tied to output pin 6, while pin 4 is NC. Its typical 24 Ω discharge path collapses 3V3A faster than held downstream capacitors. D_LDO_REV, PMEG2010ER,115, has anode at 1V8 and cathode at 3V3A to discharge TLV755 output into its input. Its published 250 mV maximum forward voltage at 100 mA is a 25°C condition; temperature and reverse leakage require board measurement. GPIO low/high-impedance sequencing and ADC/reference startup are verified separately in the firmware host harness and then physically at the connector. OPA4323IPWR replaces the unavailable OPA4320AIPWR identifier, with the standard TSSOP-14 quad pinout.
Charger, battery and standby
The official XIAO schematic powers the system from USB through its Schottky path and disconnects the battery system path with a PMOS. System load therefore bypasses the charger output during USB operation. BQ25101 uses 2.7 kΩ for 50 mA by default; asserting P0.13 LOW adds a parallel resistor to select approximately 100 mA. The 500 mAh pack specifies 100 mA standard charging. Its ideal CC duration is 5 h at 100 mA; CV adds time. Charger dissipation at USB=5 V, battery=3 V, 100 mA is about 0.2 W. Applying the datasheet 132.9°C/W JEDEC thermal resistance gives a 26.6°C junction-rise estimate, not a closed-case or cell-temperature prediction.
The charger TS input is a fixed 10 kΩ resistor in the module. IC thermal regulation monitors the charger die; the battery PCM monitors electrical faults. Charging is qualified only while actual cell temperature stays 0…45°C. Cell temperature sensing and closed-case charging measurements remain outstanding. USB input demand includes system plus charge current; verify USB configuration/startup current limits and the actual supply path voltage. Battery runtime cannot be inferred directly from 500 mAh divided by active current because the 3.6 V acquisition floor discards an unmeasured portion of capacity.
The always-powered Adafruit 4502 IMU breakout has a 10 kΩ LED branch and AP2112 regulator. Its LED alone is roughly 80–150 µA for an assumed 2.5–1.8 V forward drop; this is an estimate rather than a guaranteed range. The module's 1 MΩ +510 kΩ battery divider adds 2.78 µA at 4.2 V while its sink is held low. QSPI CS-high does not establish flash deep sleep. Firmware explicitly holds unused onboard sensor power enables low, sleeps the external IMU, and powers down the carrier analog rail; measure whole-kit System OFF current rather than quoting nRF silicon current.
Reproduction and measurement gates
Run calculate.py --output /writable/calculations.json. Run run.py --ngspice /path/to/ngspice --work /writable/power-run with ngspice's spice2poly.cm loaded through its spinit. The original vendor macro retains its license notice. The runner rejects missing output and incomplete transient analyses; buffer-results.json and rerun-results.json preserve the successful selected cases. All simulations are typical 25°C scenarios.
Before assembly release, measure (1) rail sequencing, ADC startup and GPIO back-power currents at the 3.6 V acquisition floor and temperature limits; (2) ADC reference pulse/ripple and noise with the selected reservoir; (3) VEXC load-step settling and VMID ringing with the maximum harness and simultaneous bounded sensor overload; (4) active, BLE, USB and sleep currents; (5) closed-case charger and cell temperatures. These requirements are explicit limitations of simulation, not completed physical tests.
Sources: TI REF33, Microchip MCP1501, Microchip MCP33131, AVX TAJ, TI OPAx323, TI OPAx323 original model, TI BQ25101, TI TPS22919, Nexperia PMEG2010ER, Adafruit breakout design. Official XIAO schematic and SGM2040 data are retained in component evidence / source records.